The present invention generally relates to logic circuits, and more particularly to a logic circuit which can selectively function as a toggle flip-flop or a delay flip-flop.
Every time an input signal is applied to a toggle flip-flop (hereinafter simply referred to as a T flip-flop), an output signal of the T flip-flop is inverted. On the other hand, a delay flip-flop (hereinafter simply referred to as a D flip-flop) holds and outputs an input data in synchronism with edges of a clock signal.
With the recent rapid progress in integrated circuits (ICs), the user's needs are expanding and there are demands for easy-to-use ICs in addition to the high integration density and high performance. As one conceivable method of satisfying such demands, it is possible to provide two functions in one IC.
A description will be given of a conventional D flip-flop and a conventional T flip-flop which employ the emitter-coupled logic (ECL).
FIG. 1 shows a circuit diagram of the conventional D flip-flop which employs the ECL with the so-called series gate and collector dot. The D flip-flop comprises transistors Q1 through Q22 and resistors R1 through R12. In FIG. 1, D denotes a data signal, C denotes a clock signal, V.sub.CS denotes a reference voltage, GND denotes a ground voltage of 0 V, and V.sub.EE denotes a power source voltage of -5.2 V.
FIGS. 2A and 2B respectively show a circuit portion 1 indicated by a phantom line in FIG. 1. FIGS. 2A and 2B respectively show a latch circuit, and the D flip-flop comprises two such latch circuits which are connected in series. A description will first be given of the operation of the latch circuit so as to facilitate the understanding of the D flip-flop.
In a first case where the data signal D has a high level and the clock signal C has a low level, the transistor Q1 turns ON and the transistor Q2 turns OFF. In addition, the transistor Q3 turns ON and the transistor Q6 turns OFF. Hence, a current flows through the resistor R2 as indicated by a solid arrow in FIG. 2A, and no current flows through the resistor R3. Accordingly, the level at a node A becomes low, and the level at a node B becomes high. Outputs X and X which are obtained via an emitter follower which comprises the transistors Q7 and Q8 respectively have a high level and a low level. The transistors Q9 through Q11 function as a current source.
In a second case where the data signal D has a low level and the clock signal C has a low level, the transistor Q1 turns OFF and the transistor Q2 turns ON. In addition, the transistor Q3 turns ON and the transistor Q6 turns OFF. Hence, a current flows through the resistor R3 as indicated by a phantom arrow in FIG. 2A, and no current flows through the resistor R2. Accordingly, the level at the node A is high and the level at the node B is low. The outputs X and X respectively have a low level and a high level. In other words, the data signal D is output as it is as the output X when the clock signal C has the low level.
In a third case where the data signal D has a high or low level and the clock signal C has a high level, the transistor Q3 turns OFF and the transistor Q6 turns ON. Hence, if the output X has a high level immediately before the clock signal C undergoes a transition from a low level to a high level, the transistor Q4 turns ON and the transistor Q5 turns OFF. As a result, a current flows through the resistor R2 as indicated by a solid arrow in FIG. 2B, and no current flow through the resistor R3. Accordingly, the level at the node A is low and the level at the node B is high. The outputs X and X respectively have a high level and a low level. On the other hand, if the output X has a low level immediately before the clock signal C undergoes a transition from a low level to a high level, the transistor Q4 turns OFF and the transistor Q5 turns ON. As a result, a current flows through the resistor R3 as indicated by a phantom arrow in FIG. 2B, and no current flows through the resistor R2. Accordingly, the outputs X and X respectively have a low level and a high level.
Therefore, when the clock signal C has a high level, the latch circuit holds an output state immediately before the clock signal C undergoes a transition from a low level to a high level (that is, performs a latch operation), regardless of the level of the input signal D. The following Table shows a truth table summarizing the operation of the latch circuit, where L denotes a low level, H denotes a high level and Q denotes an output level immediately before the clock signal C undergoes a transition from the low level to the high level. This designation is also used in the description hereafter.
TABLE ______________________________________ Clock C D .sup.-- D X .sup.-- X ______________________________________ L H L H L L L H L H H H L Q Q H L H Q Q ______________________________________
FIG. 3A is a block diagram of the circuit portion 1, and FIG. 3B shows latch circuits 1.sub.1 and 1.sub.2 constituting the D flip-flop shown in FIG. 1.
Next, a description will be given of the operation of the D flip-flop, by referring to FIG. 3B. FIGS. 4(A) through 4(C) are timing charts for explaining the operation of the D flip-flop, and FIGS. 5A through 5E respectively show data flows at various time intervals ta through te shown in FIGS. 4(A) through 4(C).
During the time interval ta, C=L, D=L and Q=L as shown in FIG. 5A, where it is assumed that Q=L. In this case, the latch circuit 1.sub.1 outputs the incoming low-level data signal D as it is, and the latch circuit 1.sub.2 latches a previous data signal D (assuming Q=L).
During the time interval tb, C=H, D=L and Q=L as shown in FIG. 5B. That is, the latch circuit 1.sub.1 latches the low-level signal which is output during the time interval ta, and the latch circuit 1.sub.2 outputs the incoming low-level signal as it is.
During the time interval tc, C=H, D=H and Q=L as shown in FIG. 5C. In this case, because the latch circuit 1.sub.1 latches the low-level signal, the output of the latch circuit 1.sub.1 does not change even when a high-level data signal D is received. The latch circuit 1.sub.2 outputs the incoming low-level signal as it is.
During the time interval td, C=L, D=H and Q=L as shown in FIG. 5D. In other words, the latch circuit 1.sub.1 outputs the incoming high-level data signal D as it is, and the latch circuit 1.sub.2 latches the low-level signal which is output during the time interval tc.
During the time interval te, C=H, D=H and Q=H as shown in FIG. 5E. In this case, the latch circuit 1.sub.1 latches the high-level signal which is output during the time interval td. On the other hand, the latch circuit 1.sub.2 outputs the high-level signal which is received by the transition of the clock signal C, as it is.
Therefore, the D flip-flop latches the level of the data signal D when the clock signal C undergoes a transition from a low level to a high level, and this level is held and output until the clock signal C undergoes a next transition from the low level to the high level.
Next, a description will be given of an operation of the conventional T flip-flop. The T flip-flop comprises the latch circuits 1.sub.1 and 1.sub.2 which are connected in series, and a feedback path is provided as shown in FIG. 6 to feed back an output of the latch circuit 1.sub.2 to the latch circuit 1.sub.1 FIGS. 7(A) and 7(B) are timing charts for explaining the operation of the T flip-flop, and FIG. 8 shows a circuit structure of the T flip-flop. FIGS. 9A through 9D respectively show data flows at various time intervals tf through ti shown in FIGS. 7(A) and 7(B).
During the time interval tf, C=L and Q=L. In other words, the latch circuit 1.sub.1 outputs the incoming low-level signal as it is, and the latch circuit 1.sub.2 latches a low-level signal which is output during a previous time interval.
During the time interval tg, C=H and Q=H. In this case, the latch circuit 1.sub.1 latches the low-level signal which is output during the time interval tf, and the latch circuit 1.sub.2 functions as an inverter. The latch circuit 1.sub.1 receives as an input the output Q of the latch circuit 1.sub.2 which is fed back to the latch circuit 1.sub.1.
During the time interval th, C=L and Q=H. That is, the latch circuit 1.sub.1 outputs the incoming high-level signal as it is, and the latch circuit 1.sub.2 latches the high-level signal which is output during the time interval tg.
During the time interval ti, C=H and Q=L. In this case, the latch circuit 1.sub.1 latches the high level signal which is output during the time interval th, and the latch circuit 1.sub.2 functions as an inverter.
Therefore, the T flip-flop outputs a signal which has a period two times the period of the clock signal C in synchronism with the clock signal C. The output signal of the T flip-flop is inverted for every one period of the clock signal C.
However, in the conventional logic circuits which require the functions of the D flip-flop and the T flip-flop, two independent circuits must be designed and produced to realize the functions of the D flip-flop and the T flip-flop. For this reason, the integration density and functions of the logic circuit cannot be improved, and there are problems in that it is difficult to satisfy the user's various demands and to reduce the cost of the logic circuit.
The above described problems are notable especially when D flip-flops and T flip-flops coexist within the logic circuit and the D flip-flop of the logic circuit is changed to the T flip-flop or vice versa. In this case, the mask pattern of the logic circuit must be redesigned in accordance with the change of flip-flops used, and the design and production processes must be carried out again. As a result, the development cost of the logic circuit becomes expensive, and a long time is required to develop one logic circuit to meet the user's demands. In other words, once the logic circuit is produced, the user cannot freely change the arrangement of the flip-flops within the logic circuit, and the entire logic circuit must be redesigned in order to change the arrangement of the flip-flops within the logic circuit.